BRANCH 2
Memory
What feeds the multiplier fast enough?
7 mapped nodes · qualified HBM binds · the tightest branch on the silicon side
Worth restating why this branch outranks arithmetic, because most supply-chain writing has the order backwards. Generating a token means streaming weights out of memory and multiplying them; the arithmetic done per weight read is low, so the accelerator finishes its math and waits. The scarce resource is bytes per second, not FLOPs.
And it is bytes of capacity too. Every concurrent request carries its own accumulated context, so serving more users at once raises capacity pressure at the same time. Bandwidth and capacity both live on this branch, and batching trades one for the other rather than escaping either. Qualified HBM binds because only a stacked, tested and qualified product can enter advanced packaging; package capacity is easing, HBM allocation is not.
Qualified HBM stack
binding
Why it exists
Ordinary DRAM cannot deliver the bandwidth. HBM stacks DRAM die vertically, connects them through the stack, and sits inside the accelerator package — micrometres from the logic die, because at these bandwidths the distance matters.
SK Hynix has said it sold out its entire 2026 HBM supply, with Micron similarly booked. All three have reportedly completed allocation negotiations for the whole of 2027, months early, with buyers receiving only 60-70% of requested volumes and locking supply through advance deposits. HBM4 ramps through late 2026 alongside NVIDIA's Vera Rubin and AMD's MI455X.
Relevant businesses
Worth understanding
This is the branch's binding commercial output. Nominal wafer or stacking capacity does not become usable supply until a stack meets the accelerator vendor's electrical, thermal, yield and reliability qualification. Allocation is therefore for qualified HBM, not generic memory bits.
It combines every condition for pricing power at once — three suppliers, two-to-three-year expansion cycles, no substitute, and demand scaling with accelerator units and bytes per accelerator, both rising. And it reaches the customer's product roadmap directly: if you cannot get HBM you cannot ship an accelerator, regardless of how much packaging you hold.
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HBM DRAM-die fabrication
tight
Why it exists
HBM begins as specialised DRAM die made on memory processes, with TSV structures and far more die area per usable bit than commodity memory.
This is one source of HBM's expansion lead time, not the whole of it. Clean-room capacity takes two to three years to add and competes with conventional DRAM for wafer allocation.
Relevant businesses
Worth understanding
Expanding HBM output costs a supplier more conventional DRAM output than the bit count suggests, which is part of why the three suppliers ration rather than race. Leading-edge DRAM's use of EUV is the genuine shared-capacity link to the arithmetic path.
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HBM logic base-die fabrication
available, transitioning
Why it exists
The base die terminates the stack's vertical connections and handles interface, control and test functions. With HBM4, that logic becomes materially more complex and can move onto a distinct logic process rather than being treated as another DRAM layer.
It is a separate node because its production route can diverge from the DRAM die above it. A memory vendor may make the DRAM layers while relying on a logic-foundry process for the base die, creating a separate tape-out, wafer and qualification schedule.
Relevant businesses
- HBM vendors
- logic-foundry partners
Worth understanding
This is not currently marked binding. Its importance is transitional: if HBM4 base-die complexity or foundry coordination slips, nominal DRAM-stack capacity does not translate into a qualified HBM4 product.
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HBM stacking and bonding
tight
Why it exists
The DRAM and base die must be thinned, aligned, bonded and connected vertically before they become HBM. Throughput and yield at this stage are different production problems from front-end wafer fabrication.
Stacking multiplies defect exposure: losing one die or one bond can lose the value of the stack. Higher stack heights and tighter pitches therefore raise equipment, process-control and yield demands even when wafer output is unchanged.
Relevant businesses
- SK Hynix
- Micron
- Samsung
- BESI
- assembly partners
Worth understanding
Separating this node stops “HBM capacity” from hiding two queues. More DRAM wafers do not help if bonding throughput or stack yield is the limit; more bonders do not help if qualified die are missing.
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Advanced-package integration
easing
Why it exists
HBM only delivers its bandwidth if it sits beside the logic die. CoWoS puts both on an interposer carrying the enormous connection count between them.
Capacity has gone from roughly 35,000 wafers/month in late 2024 toward a projected 130,000 by end-2026, plus 50,000-60,000 from OSAT partners. TSMC's CEO called it "extremely tight and sold out through 2026". Backend facilities are reported sold out through 2027 on 52-78 week lead times. TrendForce has the supply-demand gap narrowing from about 20% today to about 10% by end-2026.
Relevant businesses
- TSMC (CoWoS, SoIC)
- Amkor
- ASE
- SPIL
- JCET
Worth understanding
A constraint narrowing from 20% to 10% is still a constraint, but a decaying one, and decaying constraints stop conferring pricing power well before they disappear. This is the clearest case on the map of a bottleneck with a visible expiry.
Which produces the most important sequencing point in this primer: packaging is clearing into HBM, which is not clearing. An accelerator needs a packaging slot and an HBM allocation. Packaging relief delivered into a market where HBM is sold out through 2027 and buyers are rationed to 60-70% converts into exactly zero additional accelerators. The constraint everyone watches is resolving into the constraint above it.
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FC-BGA package substrates
easing
Why it exists
The finished package has to sit on something that routes thousands of connections out to the board, at high layer counts and very tight tolerances.
Was a severe bottleneck, now easing. Ibiden announced a ¥500bn capital plan for AI substrate capacity in February 2026. Ibiden, the hidden bottleneck. Substrates run 30-40% of package bill-of-materials cost in complex configurations, so this is not a trivial line.
Relevant businesses
- Ibiden ~35%
- Shinko ~18%
- Unimicron ~14%
- AT&S ~10%
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ABF film
bedrock
Why it exists
Those substrates are built from Ajinomoto Build-up Film — a material with essentially one supplier, and that supplier is a food company.
Not binding today. It binds precisely in the scenario where everything else goes right. An AI accelerator uses roughly ten times the ABF film of a standard PC processor, and Ibiden has said it has film secured for current guidance but "not yet secured materials to accommodate potential upside".
Relevant businesses
- Ajinomoto, effectively alone
Worth understanding
That quote is the exact shape of a latent constraint: adequate for the plan, inadequate for the upside. Like EUV, this is a monopoly of accumulated process knowledge rather than of capacity, and it cannot be routed around at any price on a useful timeframe.
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Reading this branch
Its binding product sits immediately before the branch merge. Qualified HBM has no substitute inside the current accelerator architecture, so relief elsewhere cannot route around its allocation.
It contains a decaying constraint and a hardening one, stacked. Packaging is easing on a schedule. HBM is not. Reading them as equivalent — which almost all commentary does, since both are “AI supply chain shortages” — produces exactly the wrong forward view.
Its slowest mapped material comes from a food company. Worth saying plainly, because it is the best illustration of why a demand-derived path beats a parts list: nothing about Ajinomoto would ever surface in a screen of AI companies, yet its film enables the package substrate.