The chain
Inference needs both memory bandwidth and capacity. HBM brings the memory close enough to the logic, but it also joins usable supply to stacking yields, packaging slots and a three-company qualification pool.
What matters now
An accelerator needs both. Capacity arriving at CoWoS cannot clear an allocation book at the memory supplier.
SK hynix says equal output requires at least twice the production capability of ordinary DRAM. Bit counts understate the sacrifice.
When conventional DRAM earns more per wafer, the same clean-room capacity has a reason to move even while HBM remains strategically essential.
How this gate formed
A selected memory chronology. Each event changes the usable supply pool, the layer doing the gating, or the incentive to allocate the shared base.
Qualified HBM3 enters production
SK hynix begins mass production for NVIDIA's H100 after NVIDIA completes performance evaluation. Qualification—not nominal DRAM capacity—defines the usable pool. SK hynix
The bottleneck moves into assembly
Accelerator demand outruns CoWoS and HBM supply. The industry can fabricate more logic than it can assemble into a usable accelerator. SemiAnalysis
The book closes; capital responds
SK hynix says planned 2024 HBM output is sold out, then commits more than ₩20 trillion to M15X. The response is large, but the fab clock is still long. allocation · M15X
The allocation incentive turns
TrendForce estimates that DDR5 64GB RDIMM revenue per wafer overtook HBM in 1Q26. The shortage need not end for the allocation economics to change. TrendForce
The current read
The first ring controls the branch
HBM is close to demand and supplied by three qualified makers. Packaging is an enabling complement, not a substitute. Relief downstream creates no accelerator unless an HBM allocation arrives with it.
Contracts meet a shared base
The next question is whether long-duration purchase floors and deposits prevent the usual memory reversion—or simply partition which products and customers absorb it.
Supply must beat two growth rates
- Qualified HBM capacity additions land.
- Bits per stack rise faster than bandwidth demand per accelerator.
- Yield and stacking throughput improve without consuming the conventional base faster.
Four disconfirming signals
- Allocation books reopen materially.
- Spot and contract prices converge downward.
- Packaging again becomes the binding gate.
- Architectural efficiency reduces memory demand per served token.