The supply chain behind AI compute
Start at operational AI compute capacity and follow what it physically requires. This is a dated, non-exhaustive view of the terrain, not a perimeter around the theme.
Follow the arrows toward the centre. Each supply node is an economically supplied input, product or process that enables the next. Radial distance is layout, not a fixed production stage.
READ THE CONNECTION. Solid paths show supply or process flow; a physical merge appears only where several streams meet at the same downstream node. Dashed paths show shared manufacturing capacity. A company present at several nodes is neither.
The centre is not a building or a pile of servers. It is capacity that can produce tokens: accelerators and memory assembled into working racks, connected by a working network, installed at a viable site, energised continuously and kept within thermal limits.
Inference streams model weights from memory for every token, so memory bandwidth can limit throughput before arithmetic. Models that exceed one accelerator turn that memory problem into a network problem. Every operation also consumes power and produces heat, while latency-sensitive inference constrains where that power must be available. Those physical requirements produce the five branches below.
Critical is not the same as constrained. The useful questions are which node limits each path now, how long expansion takes, and whether substitution can remove the pressure before new supply arrives.
| Branch | Current read | What changes—or comes next |
|---|---|---|
| 1 Arithmetic | No current gate. Commercial accelerator supply is limited after the logic die. | Test becomes the next arithmetic-side watch if memory and integration clear. |
| 2 Memory | Qualified HBM is the tightest silicon-side output. | More qualified stacks, less bandwidth demand per accelerator, or architectural substitution. |
| 3 Movement | The optical limit has moved from EML lasers toward InP substrates. | Laser and substrate capacity, or an architecture that uses fewer EMLs. |
| 4 Energy | Utility power delivery binds overall at interconnection. | Transmission and generation additions plus interconnection approval and energisation—or a project-specific on-site bypass. |
| 5 Place | Site development and skilled trades are tight; timing mostly inherits Energy. | More executable sites, permitting throughput and field capacity. |
Manufacturing and delivery run on different clocks. Semiconductor, transformer and generation-equipment suppliers have identifiable capacity programmes. Utility delivery depends on interconnection, transmission, generation and approvals that do not clear on the same schedule.
Clearing one node exposes the next. Packaging relief exposes qualified HBM; more EML capacity pushes attention toward InP; test becomes visible if the silicon-side constraints ease.
Tightness and rent are separate. Durability, supplier concentration and resistance to substitution determine who captures the scarcity. A sharp AI-capex slowdown would ease most manufactured constraints together.
The main map keeps the physical paths and their real merge points in view. Open a branch to follow its nodes, owners, constraint state and current reading in detail.
9 mapped nodes · does not bind · joins memory at advanced-package integration
The branch most people think is constrained, and it has not been for about two years. In 2023 leading-edge foundry allocation was the gate. It cleared. A tested logic die can now exist in inventory while the accelerator cannot ship because qualified HBM or an integration slot is missing.
That distinction is why the logic die and the accelerator package are separate nodes. Arithmetic supply reaches a usable product only after it meets memory and package integration; commercial accelerator output is now gated after the logic die.
7 mapped nodes · qualified HBM binds · the tightest branch on the silicon side
Worth restating why this branch outranks arithmetic, because most supply-chain writing has the order backwards. Generating a token means streaming weights out of memory and multiplying them; the arithmetic done per weight read is low, so the accelerator finishes its math and waits. The scarce resource is bytes per second, not FLOPs.
And it is bytes of capacity too. Every concurrent request carries its own accumulated context, so serving more users at once raises capacity pressure at the same time. Bandwidth and capacity both live on this branch, and batching trades one for the other rather than escaping either. Qualified HBM binds because only a stacked, tested and qualified product can enter advanced packaging; package capacity is easing, HBM allocation is not.
11 mapped nodes · binds in the optical path · the constraint is still moving upstream
Two facts from the output make this branch grow faster than the others. Models exceed one accelerator's memory, so a model that does not fit must be sharded and the shards exchange state for every token. And serving at scale means thousands of accelerators, where the fraction of time each spends waiting for the others is a major determinant of cluster efficiency.
Which produces the structural fact: interconnect scales faster than compute. Each generation raises the bandwidth every chip needs to reach every other chip, so optical demand grows faster than accelerator unit demand. Reasoning about optics from GPU shipments systematically undercounts—twice over, because lasers per module rise with lane count as well. The optical constraint has moved from module assembly to EML lasers and now toward InP substrates.
7 mapped nodes · utility power delivery binds at interconnection · the grid path's terminal constraint
This branch contains two different clocks. Transformers, switchgear, generation equipment, facility distribution and cooling are manufactured capacity: capital can expand them, but only on multi-year schedules. Utility power delivery is not only an equipment problem. Studies, transmission, generation additions, approvals and energisation do not move on the same clock.
That difference is the branch's most consequential feature. Utility delivery currently binds at interconnection, while on-site generation offers a project-specific bypass that creates its own equipment constraints. Efficiency and heat removal matter because they determine how much operational compute fits behind each available megawatt.
4 mapped nodes · site development and trades enable fit-out · absorbs every upstream delay
Trivially, the accelerators need a building. Less trivially, this is the branch that has to be assembled last, which means it absorbs every delay above it. A site finished ahead of utility service strands capital; a site finished behind its accelerator delivery strands silicon.
Site development, construction and fit-out, and skilled trades remain separate economic inputs because any one can hold up an otherwise ready facility. Place is where mismatched delivery schedules across the rest of the map become a project that cannot yet operate.
A physical merge joins separately made streams into one system. Shared capacity means different products draw on the same production capability. A company operating in several verticals is neither by itself.
| Point or capability | Paths | What actually touches |
|---|---|---|
| EUV lithography systems | Arithmetic · memory · movement | Shared capacity. Different wafer products draw on the same scarce tool class. |
| Advanced-package integration | Arithmetic · memory | Physical merge. Logic die, qualified HBM and substrate become an accelerator package. |
| Server and rack integration | Arithmetic · memory · movement | Physical merge. Accelerator packages, adapters and the network become working racks. |
| Operational AI compute capacity | All five | Final merge. Racks, network, power, cooling and a viable site must all be present. |