BRANCH 1
Arithmetic
What does the multiplying?
5 rings deep · does not bind · contains two of the tree's convergence points
The branch most people think is constrained, and it has not been for about two years. Deepest of the five, with five rings of plumbing between demand and bedrock, and every ring is a manufacturing problem that capital is actively solving. In 2023 this branch was the constraint — foundry allocation was the gate. It cleared, and the constraint moved to branch 2.
L1
Accelerator silicon
rent
Why it existsSomething has to perform the matrix multiplications. This is the layer everyone means when they say "AI chips."
NVIDIA holds roughly 70-75% of data centre AI accelerator revenue in 2026, down from a peak near 87% in 2024. The custom side runs through two co-design houses: Broadcom at roughly 70-75% of custom ASIC co-design (Google TPU, Meta MTIA) and Marvell at 20-25% (AWS Trainium and Inferentia, Microsoft Maia) — together about 95% of that market. Tom's Hardware, custom ASIC state of play.
Not constrained by design or fabrication capacity. Gated entirely by branches 2 and 3. An accelerator program is limited by HBM allocation and packaging slots, not by anyone's ability to design or fabricate the logic die.
Worth understandingCustom ASIC shipments are outgrowing merchant GPUs for the first time — TrendForce projects 44.6% against 16.1% in 2026. That matters to the tree in a specific way: custom programs sit second in the queue for constrained inputs. When packaging or memory is short, the vendor with the largest committed volume is served first. The custom-silicon story and the bottleneck story are entangled, not independent.
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L2
Co-design and IP
rent
Why it existsNobody designs a leading-edge accelerator from nothing. It is assembled from licensed blocks using licensed tools.
Synopsys and Cadence are an EDA duopoly with Siemens EDA third. Arm supplies CPU IP. The high-speed SerDes that moves data between chips is a chokepoint of expertise rather than capacity.
Not constrained in any capacity sense — software has no lead time. But it is a rent-capturing layer with extraordinary economics and near-total switching-cost lock-in.
Worth understandingThis node is the cleanest proof in the tree that tightness and rent are separate variables. EDA gates nothing and earns enormously. Any framework that equates "bottleneck" with "where the money is" fails here immediately.
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L2 · serves branches 1, 2, 3
Logic foundry
rent tight
Why it existsThe design has to become silicon, at N3 today and N2 next.
TSMC, and effectively only TSMC for leading-edge AI silicon. Samsung and Intel matter for optionality and for policy, both structurally behind at the leading edge.
Tight, but not the gate. This is the correction to make early, because the popular mental model is still "the shortage is chips." Wafer capacity at N3/N5 is not what limits AI accelerator supply. Packaging and memory are, which is branch 2.
Worth understandingThe industry solved the wafer problem before it solved the assembly problem. A leading-edge fab is enormously expensive but well-understood and has been scaling for decades. What sits on branch 2 is newer, less automated, and was not built for this volume.
This node is the tree's most concentrated convergence point. TSMC fabricates the logic here, packages the memory on branch 2, and packages the photonics on branch 3. Three of five branches pass through one company — structural rather than commercial, and no second-sourcing at other levels routes around it.
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L3
Fab equipment
tight
Why it existsFabs are assembled from tools, and the tools have longer lead times than the fabs do.
Deposition and etch is Applied Materials, Lam Research and Tokyo Electron. Metrology is KLA. Hybrid bonding — which branch 2 depends on — is BE Semiconductor. The compound-semiconductor epitaxy reactors that branch 3 depends on are Aixtron and Veeco.
Worth understandingThis node is where branch 1 reaches back into the others. The tools that make HBM stacks and the reactors that grow laser material both sit here, so equipment tightness propagates across branches that otherwise look independent.
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L3
Test
tight
Why it existsEvery die has to be verified before it goes into a package that costs more than the die does.
Tight, and the most plausible candidate for the next silicon-side bottleneck nobody is watching.
Worth understandingAI accelerators are enormous die with long test times, and test capacity scales with neither wafer starts nor packaging capacity. It is a separate queue with its own equipment lead times, and it becomes visible the moment the two constraints in front of it clear. If branches 2 and 3 resolve on schedule in 2027-28, this is the most likely thing standing behind them.
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L3
Wafers and process chemicals
open
Why it existsThe fab consumes polished silicon wafers, photoresist, specialty gases and ultrapure chemicals.
Not constrained. Standard silicon wafers are not the problem anywhere in this tree. The compound substrates that are a problem sit on branch 3, not here — which is a distinction worth holding, because "wafer supply" language gets applied to both.
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L4 · serves branches 1, 2
EUV lithography
bedrock rent
Why it existsBelow a certain feature size there is no other way to pattern a wafer.
ASML says it is raising capacity roughly 30% in each of the next two years, cutting EUV build-and-test cycle time from about 22 weeks toward 15 or 16, and is close to fully booked on EUV for 2027 with a substantial 2028 order book. Component shortages inside its own supply chain still limit output.
Worth understandingWhen the tool vendor is booked two years out, capacity decisions taken today do not produce wafers until 2028. That sets the outer bound on how fast anything downstream can expand — on this branch and on branch 2, because leading-edge DRAM now needs EUV too.
This is a monopoly of accumulated expertise rather than of capacity, which behaves differently from a full order book. An order book clears when capacity arrives. An expertise monopoly does not clear at all; it just becomes less binding when demand growth slows. That makes it the most durable position on this branch and simultaneously the one least likely to be mispriced, since everybody already knows.
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L5 · bedrock
EUV optics and light source
bedrock
Why it existsASML does not make the hardest parts of its own machine. The mirrors — the flattest surfaces manufactured anywhere — come from Carl Zeiss SMT, and the high-power CO2 drive lasers from Trumpf, with the light source itself from ASML's own Cymer.
Worth understandingThis is the true floor of branch 1, and it is one company deep. When ASML says component shortages in its own supply chain limit output, this is substantially what it means. The bedrock beneath the world's most important monopoly is a privately-held German optics firm that cannot be second-sourced, cannot be bought, and cannot be scaled by anyone else's capital.
It is also the clearest demonstration of why deriving the tree beats enumerating it. Nothing about Zeiss would ever surface in a screen of AI companies, and it sits five steps from every token generated.
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Reading this branch
It is deep, and depth is protective. Five rings between inference demand and the unfixable part, and every intermediate ring is a manufacturing problem with an identified owner spending capital and a stated arrival date. That is the profile of a branch that clears.
Its two hard nodes serve other branches. ASML gates branch 2's DRAM as well as this branch's logic; TSMC gates branch 2's packaging and branch 3's photonics. The arithmetic branch is not itself constrained, but it contains two of the tree's most important convergence points — a different kind of importance.
Watch test. If branches 2 and 3 clear on schedule in 2027-28, test is the most likely thing standing behind them, and it currently attracts almost no attention.
BRANCH 2
Memory
What feeds the multiplier fast enough?
4 rings deep · binds at the first ring · the tightest branch on the silicon side
Worth restating why this branch outranks branch 1, because most supply-chain writing has the order backwards. Generating a token means streaming weights out of memory and multiplying them; the arithmetic done per weight read is low, so the accelerator finishes its math and waits. The scarce resource is bytes per second, not FLOPs.
And it is bytes of capacity too. Every concurrent request carries its own accumulated context, so serving more users at once — the thing that makes inference economical — raises capacity pressure at the same time. Bandwidth and capacity both live on this branch, and batching trades one for the other rather than escaping either. It is also why HBM sits physically beside the logic die rather than on the board, which drags advanced packaging onto this branch as a co-requirement rather than a separate step.
L1
HBM
binding rent
Why it existsOrdinary DRAM cannot deliver the bandwidth. HBM stacks DRAM die vertically, connects them through the stack, and sits inside the accelerator package — micrometres from the logic die, because at these bandwidths the distance matters.
SK Hynix has said it sold out its entire 2026 HBM supply, with Micron similarly booked. All three have reportedly completed allocation negotiations for the whole of 2027, months early, with buyers receiving only 60-70% of requested volumes and locking supply through advance deposits. HBM4 ramps through late 2026 alongside NVIDIA's Vera Rubin and AMD's MI455X.
Worth understandingThis is the shallowest binding node in the tree. It sits one ring from inference demand. There is almost nothing between a user's token and a three-supplier oligopoly.
It combines every condition for pricing power at once — three suppliers, two-to-three-year expansion cycles, no substitute, and demand scaling with accelerator units and bytes per accelerator, both rising. And it reaches the customer's product roadmap directly: if you cannot get HBM you cannot ship an accelerator, regardless of how much packaging you hold.
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L2
DRAM fabrication and stacking
tight
Why it existsHBM is DRAM die, thinned, stacked, and bonded with through-silicon vias.
This is where HBM's expansion lead time actually comes from. Capacity here takes two to three years to add, which is the floor on how fast the node above it can ease.
Worth understandingHBM stacking has poor yields relative to ordinary DRAM and consumes far more wafer area per usable bit. Expanding HBM output costs a supplier more conventional DRAM output than the bit count suggests, which is part of why the three of them have been willing to ration rather than race. It is also why this node reaches back into branch 1: leading-edge DRAM now needs EUV.
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L2 · serves branches 2, 3
Advanced packaging
decaying
Why it existsHBM only delivers its bandwidth if it sits beside the logic die. CoWoS puts both on an interposer carrying the enormous connection count between them.
Capacity has gone from roughly 35,000 wafers/month in late 2024 toward a projected 130,000 by end-2026, plus 50,000-60,000 from OSAT partners. TSMC's CEO called it "extremely tight and sold out through 2026". Backend facilities are reported sold out through 2027 on 52-78 week lead times. TrendForce has the supply-demand gap narrowing from about 20% today to about 10% by end-2026.
Worth understandingA constraint narrowing from 20% to 10% is still a constraint, but a decaying one, and decaying constraints stop conferring pricing power well before they disappear. This is the clearest case in the tree of a bottleneck with a visible expiry.
Which produces the most important sequencing point in this primer: packaging is clearing into HBM, which is not clearing. An accelerator needs a packaging slot and an HBM allocation. Packaging relief delivered into a market where HBM is sold out through 2027 and buyers are rationed to 60-70% converts into exactly zero additional accelerators. The constraint everyone watches is resolving into the constraint above it.
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L3
Package substrate
decaying
Why it existsThe finished package has to sit on something that routes thousands of connections out to the board, at high layer counts and very tight tolerances.
Was a severe bottleneck, now easing. Ibiden announced a ¥500bn capital plan for AI substrate capacity in February 2026. Ibiden, the hidden bottleneck. Substrates run 30-40% of package bill-of-materials cost in complex configurations, so this is not a trivial line.
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L4 · bedrock
ABF film
bedrock
Why it existsThose substrates are built from Ajinomoto Build-up Film — a material with essentially one supplier, and that supplier is a food company.
Not binding today. It binds precisely in the scenario where everything else goes right. An AI accelerator uses roughly ten times the ABF film of a standard PC processor, and Ibiden has said it has film secured for current guidance but "not yet secured materials to accommodate potential upside".
Worth understandingThat quote is the exact shape of a latent constraint: adequate for the plan, inadequate for the upside. Like EUV, this is a monopoly of accumulated process knowledge rather than of capacity, and it cannot be routed around at any price on a useful timeframe.
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Reading this branch
It is the shallowest branch that binds, and that is what makes it dangerous. Four rings total, and the binding node is at the first. Compare branch 1, where five rings of plumbing sit between demand and bedrock.
It contains a decaying constraint and a hardening one, stacked. Packaging is easing on a schedule. HBM is not. Reading them as equivalent — which almost all commentary does, since both are “AI supply chain shortages” — produces exactly the wrong forward view.
Its bedrock is a food company. Worth saying plainly, because it is the best illustration of why a demand-derived tree beats a parts list: nothing about Ajinomoto would ever surface in a screen of AI companies, and it sits four steps from every token generated.
BRANCH 3
Movement
What connects chips that must share the work?
4 rings deep · binds at the third · and the constraint is still climbing outward
Two facts from the root make this branch grow faster than the others. Models exceed one accelerator's memory, so a model that does not fit must be sharded and the shards exchange state for every token — an internal memory transfer becomes a network transfer. And serving at scale means thousands of accelerators, where the fraction of wall-clock time each spends waiting for the others is the single largest determinant of cluster efficiency.
Which produces the structural fact: interconnect scales faster than compute. Each generation raises the bandwidth every chip needs to reach every other chip, so optical demand grows faster than accelerator unit demand. Reasoning about optics from GPU shipment counts systematically undercounts — twice over, because lasers per module rise with lane count as well.
L1
Optical modules
tight
Why it existsThe pluggable transceiver converts electrical signals into light and back. Volume is 800G today with 1.6T ramping and 3.2T next.
Chinese vendors hold seven of the top ten seats. Innolight and Eoptolink together supply roughly 60% of NVIDIA's 800G demand, Innolight alone above 50% of its 800G procurement.
The market is short: constrained by shortages of upstream EML laser chips and isolators, 1.6T shipments in 2026 are projected at about 15 million units against demand implying roughly 25 million — a gap of about 10 million units. LightCounting, April 2026.
Worth understandingModule assembly capacity is not what is short. The modules cannot be built because the parts inside them cannot be bought. That distinction is the whole reason to descend two more rings, and it determines who captures the scarcity — which is not the assemblers. They are prepaying to secure inputs, and prepaying is what capturing less of a shortage looks like.
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L1
Switch silicon
rent
Why it existsSomething has to route the packets. Broadcom's Tomahawk and Jericho lead the merchant market; NVIDIA sells Spectrum-X and Quantum InfiniBand as part of an integrated system rather than as merchant silicon.
Not constrained. But this is where the architecture gets decided. Switch silicon dictates whether a link is copper or optical, at what rate, in what form factor. Small share of cost, enormous share of control.
Worth understandingNVIDIA's networking position is not really a networking business; it is a mechanism for selling the rack as a unit. When the compute vendor also supplies the fabric, every supplier below designs to a schedule set by someone else's product cycle.
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L1 · serves branches 3, 4
Copper and connectors
tight
Why it existsThere are two networks here with different physics. Scale-up connects accelerators inside a rack at the highest bandwidth over the shortest distance — NVIDIA's NVLink spine uses thousands of copper pairs. Scale-out connects racks across a building, which means optics.
Constrained by physics rather than capacity, and that boundary is the interesting part.
Worth understandingThe copper/optics boundary is a moving line worth watching directly. Every generation raises the signalling rate, which shortens copper's usable reach. Simultaneously the scale-up domain grows larger, which lengthens the distances required. Those two trends point in opposite directions, and the point where copper stops working is where optics starts getting paid.
Copper as a material is also shared with branch 4, where it goes into transformer windings and busway. Two branches, one metal.
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L1
PCB and low-loss laminate
tight
Why it existsThese signals have to travel on boards engineered for very low loss at very high frequency.
Selectively tight at the top end. Very high layer counts in low-loss materials are short, and the specialty laminates are tighter than the boards.
Worth understandingA quiet second-order constraint that appears in lead times before it appears in commentary — which makes it a reasonable early-warning instrument for the branch as a whole.
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L2
Module internals
tight
Why it existsInside every module: a DSP, a driver and transimpedance amplifier, optical assembly and alignment, isolators, and the laser chips one ring further out.
Tight, with isolators specifically named alongside lasers in the shortage reporting — a reminder that a bill of materials fails at its scarcest line, not its most expensive one.
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L3
EML lasers
binding
Why it existsSomething has to make the light. For 800G and 1.6T datacentre links that means electro-absorption modulated lasers, one per lane. A 1.6T module at 200G per lane needs eight of them.
This is where the optical bottleneck actually lives, and it is tightening rather than easing. Lumentum is currently the only supplier shipping 200G-per-lane EMLs at volume — the exact part 1.6T requires. EE Times Asia. Lead times extend beyond 2027, and NVIDIA committed roughly $4bn to Lumentum and Coherent, locking supply and pushing rivals past 2027. reported May 2026. Prepayments from Innolight, Eoptolink and TFC rose from ¥172m to ¥2.27bn in Q1 2026, a thirteen-fold increase.
Worth understandingTwo signals, from opposite sides of the market, saying the same thing. A thirteen-fold rise in prepayments is a price signal from people with better information than the market — that is what conviction about scarcity looks like on a balance sheet. And a customer does not invest four billion dollars in two component suppliers to secure a component it expects to be plentiful.
Then the mechanism that matters most. Vertical integration inverts in value when the input is what is scarce. Owning laser fabs is a capital burden and a margin drag when lasers are abundant — the ordinary state, and the one most models are calibrated on. When lasers are the constraint, in-house supply is not a cost centre; it is an allocation that competitors are queuing and prepaying years early to obtain.
The inversion is not permanent, and its temporariness is the risk. The question is duration, and duration is set by epitaxy and substrate lead times — not by anything the module vendors control.
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L4 · bedrock
Indium phosphide substrate
bedrock
Why it existsEML lasers are grown on indium phosphide, and the supplier set is two names deep.
Indium phosphide shortage has emerged as the AI optical interconnect bottleneck TrendForce, 2026-08-06. That is the constraint arriving at the floor of this branch.
Worth understandingMaterial constraints behave differently from capacity constraints. A fab takes two to three years. An epitaxy line takes longer. A new compound-substrate supplier needs a decade of process learning and customer qualification. When a material binds, it binds for longer than anything downstream of it — and there is nothing investable further out.
Note what the sequence says. The constraint on this branch has climbed twice in about two years: module assembly, then laser chip, now substrate. Each move went closer to the raw material, into a narrower supplier set, with a longer expansion lead time. That is the opposite direction from branch 1, and it relocates the value: when a constraint moves downstream, value goes to whoever integrates; when it climbs, value goes to whoever owns the input.
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The threat that does not come from below: co-packaged optics
Not a node on this branch — a demand-side release valve on it. Instead of a pluggable module at the switch faceplate, the optical engine is integrated into the switch package beside the ASIC. NVIDIA ships Quantum-X InfiniBand in early 2026 and Spectrum-X Photonics Ethernet in the second half NVIDIA, claiming 4x fewer lasers, 3.5x better power efficiency, and roughly 40MW saved in a large deployment.
“4x fewer lasers” is the headline that matters to anyone holding optical exposure, and it needs care in three directions. It applies to the switch side of the link, not the whole link — the accelerator end and the enormous installed base of pluggable ports do not disappear. NVIDIA's own announcement names pluggable vendors as continuing partners: Coherent, Eoptolink, Fabrinet and Innolight appear in the same release. And fewer lasers per port is not fewer lasers — demand scales as ports × lasers-per-port, so if ports grow faster than 4x over the transition, aggregate laser demand still rises. Whether CPO reduces total laser demand is an arithmetic question about two growth rates, not a qualitative one, and most commentary treats it as qualitative.
Silicon photonics is the more consequential version of the same question, because it replaces per-lane EMLs with a smaller number of external light sources. Both are real, both move slower than their announcements imply, and neither is settled inside 2027.
Reading this branch
The constraint has climbed twice in about two years: module assembly → EML laser chip → InP substrate. Each move went closer to the raw material, into a narrower supplier set, with a longer expansion lead time. A reader who learned the shape in 2024 is watching the wrong ring.
Upward migration relocates the value. When a constraint moves downstream, value goes to whoever integrates the scarce combination. When it climbs, value goes to whoever owns the input. That is why the direction of travel matters and not merely the fact of movement.
The genuine risk is not competition — it is architecture. Nothing here is threatened by another module vendor. It is threatened by CPO and, more seriously, by silicon photonics removing the need for per-lane EMLs. That risk resolves on an engineering schedule rather than a capacity one, which makes it harder to forecast and easier to be blindsided by.
BRANCH 4
Energy
What powers it, and removes the heat?
3 rings deep · terminal at the first · the only branch whose constraint is not a manufacturing problem
Everything on branches 1 through 3 is a manufacturing constraint: someone builds a factory, learning curves apply, capacity arrives on a schedule money can compress. This branch is not that, and that difference is the most consequential structural fact in the primer. It is also the shallowest branch in the tree — its terminal constraint sits at the first ring, with essentially no plumbing between inference demand and the thing that cannot be fixed.
L1 · terminal · serves branches 4, 5
Grid interconnection
binding
Why it existsNothing runs without a connection to the transmission system. Everything on branches 1 through 3 is a manufacturing constraint: someone builds a factory, learning curves apply, capacity arrives on a schedule money can compress. This is not that. A data centre needs a utility study, a queue position, regulatory approval, transmission that may not exist, and generation that may not have been built. Money accelerates almost none of those steps, and several are controlled by parties with no commercial interest in speed.
Interconnection queues run four to seven years in many US markets, beyond five in many regions. Berkeley Lab, Queued Up 2026 tracks the queue: about 2,060 GW of generation and storage was actively waiting at the end of 2025, and of everything that entered between 2000 and 2020, 13% had reached commercial operation and 75% had been withdrawn. Grid capacity for existing data centre projects is largely committed through 2030 in most primary US markets. And capacity under construction in the eight primary US markets declined in 2025 for the first time since 2020, on permitting, zoning and power procurement delays.
Worth understandingThat last item is the most important single data point in this primer. Data centre construction slowed while demand accelerated. That is not a demand signal, and reading it as one inverts the causality.
And this node is terminal, not merely severe. In a tree, clearing a node exposes the node beneath it. This one has nothing behind it. Power is not a stage the constraint passes through on its way somewhere else; it is where the constraint arrives and stays. You can buy accelerators you cannot energise.
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L1 · the bypass
On-site generation
tight
Why it existsEntirely because the queue exists. Generate at the site, skip the interconnection.
Roughly 101 GW of on-site natural gas generation has been announced by data centre developers specifically to bypass interconnection bottlenecks. Bloom Energy's product backlog reached about $6bn entering 2026, up more than 2.5x year over year, inside a total backlog near $20bn including services; about $7.65bn of data-centre contracts landed in a single 90-day window in early 2026, and a roughly $5bn arrangement in June 2026 anchored by a $2.65bn agreement with AEP. Bloom Energy, Q2 2026. Manufacturing is expanding toward 2 GW of annual capacity by end-2026, described in trade coverage as necessary but likely insufficient against the signed pipeline.
Worth understandingThe product being sold is time, not electricity. A hyperscaler with accelerators on order and no interconnection loses revenue per day of delay. On-site generation converts a four-to-seven-year wait into months, which is why the price per kilowatt can sit well above grid power without the customer objecting: the comparison is not against grid power, it is against nothing.
This is a bypass, not a fix. It routes around the terminal node for individual projects without clearing it. 101 GW announced against manufacturing capacity in low single-digit gigawatts per year is a release valve far too small for the pressure — which is simultaneously why the constraint persists and why the suppliers are sold out.
So the analytical question here is throughput, not demand. The contracts have settled demand. Backlog growth of 2.5x against capacity growing toward 2 GW is the arithmetic that decides whether a signed pipeline becomes revenue or becomes a queue of its own.
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L1
Power inside the building
tight
Why it existsGetting power to the site is half the problem. The other half is moving it from the building feed to the chip: UPS, busway, distribution, rack conversion, board-level regulation.
Rack power is going from tens of kilowatts to hundreds. NVIDIA's Kyber generation is specified around 600 kW per rack with all-liquid cooling for H2 2027, and the industry is moving to 800 volt DC distribution to serve it. Vertiv, Schneider, Eaton and Delta have commercial 800VDC products slated for the second half of 2026. At 800VDC the same power moves at roughly 1,250 amps, cutting copper use by about 45% and lifting end-to-end efficiency from around 83% to 92% or better. Data Center Dynamics.
Worth understandingAn efficiency gain from 83% to 92% is not marginal when power is the binding constraint. It is roughly a tenth more compute from the same interconnection. When the scarce input is megawatts, efficiency at every conversion step converts directly into capacity — which makes this unglamorous node strategically valuable in this cycle specifically, and was not true in any previous one.
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L1 · serves branches 4, 5
Heat removal
tight
Why it existsEvery watt delivered is a watt to remove. Air cooling is finished at these densities; direct-to-chip liquid is the standard for new AI deployments.
Notably unconsolidated by this tree's standards — the top seven hold roughly 35% of the liquid cooling market. Cooling distribution unit capacity is now a first-order design parameter rather than a facilities detail, with CDU lines spanning roughly 70 kW to 1.35 MW per unit.
Worth understandingThe scarce resource is not the equipment. It is the people who can design and commission a liquid loop at scale, and that does not respond to capital on any useful timeframe. Which is why this node shares its bedrock with branch 5 — the same skilled trades.
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L2
Generation equipment
binding
Why it existsThe queue is long partly because the generation to serve it has not been built.
GE Vernova's gas turbine backlog reached 100 GW in Q1 2026, up from 83 GW at end-2025, after signing 21 GW of new agreements and booking $2.4bn of data centre electrification orders in a single quarter. GE Vernova, Q1 2026. Siemens Energy booked 15 GW in a quarter, with lead times running three years or more.
Worth understandingA turbine ordered today delivers around 2029. When the fastest grid-scale generation option has a three-year-plus lead time and the interconnection behind it takes four to seven years, the operator faces the sum, not the larger of the two. That sum is why the bypass exists at all, and why buyers pay a large premium per kilowatt for something that arrives in months.
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L2
Grid equipment
binding rent
Why it existsPower has to be stepped, switched and carried between generation and load. Transformers, switchgear, breakers, cable.
High-power transformer lead times went from 24-30 months pre-2020 to about five years today. Siemens Energy's grid order backlog hit a record €51bn with transformer orders up 28%, and new transformer and switchgear capacity is spoken for until 2030. Siemens Energy, Q3 FY2026. GE Vernova closed its $5.3bn purchase of the remaining half of Prolec GE in February 2026.
Worth understandingA five-year transformer lead time is longer than the AI capex cycle that created the demand. This is the node where the constraint most plainly outlasts the thing constraining it, and where a project timeline can be set by a piece of equipment nobody in the AI conversation ever mentions.
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L3 · bedrock · serves branches 3, 4
Electrical steel, copper, winding labour
bedrock
Why it existsTransformer manufacturing needs grain-oriented electrical steel, large volumes of copper, and skilled winding labour. All three have multi-year lead times of their own and far less attention than anything above them.
Worth understandingThis is the floor of branch 4, and it is where the branch touches branch 3 — copper goes into both transformer windings and cable assemblies. A copper squeeze would hit the movement branch and the energy branch simultaneously, which is exactly the kind of correlation a branch-by-branch view is built to miss.
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Reading this branch
It is the shallowest branch in the tree and its first ring is terminal. Almost nothing sits between inference demand and a constraint that cannot be cleared with money.
Two of its constraints outlast the cycle that created them. Transformers booked to 2030 and interconnection committed to 2030. If AI capex moderates in 2028, these are still tight — which makes them the least cyclical exposures anywhere in the tree, and the sharpest contrast with every silicon-side node.
Efficiency is capacity here. The 800VDC transition, liquid cooling and better conversion all convert directly into more compute per interconnection, which reframes several dull-looking nodes as strategically important — but only while the terminal constraint holds.
BRANCH 5
Place
What houses it, and who builds that?
3 rings deep · inherits its tightness from branch 4 · and shares its bedrock
Trivially, the accelerators need a building. Less trivially, this is the branch that has to be assembled last, which means it absorbs every delay above it. A shell finished ahead of its interconnection is stranded capital; a shell finished behind its accelerator delivery is stranded silicon.
L1
Shells, land and water
tight
Why it existsThe accelerators need a building with power, cooling and network. Less trivially, this is where branch 4's abstract constraint becomes a concrete non-event: a site that does not get built.
Constrained by inputs rather than capital — land near power and fibre, water rights, and local permitting, the last of which has become political in several primary markets.
Worth understandingThe 2025 decline in capacity under construction shows up here first. This node is where "the queue is long" stops being a statistic and becomes a project that did not start.
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L1
Rack integration and ODM
open, rising
Why it existsSomebody has to build the servers and racks: board assembly, integration, plumbing, test, burn-in, and shipping something that works.
Not constrained by capacity. Gated by component availability from branches 1 through 3, and increasingly by rack-integration and liquid-loop test capability.
Worth understandingAs racks become integrated systems rather than boxes of servers, the ability to build, plumb and test a complete liquid-cooled rack becomes a real capability rather than a commodity service. A moat is forming in a node that was, until recently, thin-margin assembly — a rare direction of travel, and worth watching for that reason alone.
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L2
Electrical and mechanical construction
tight
Why it existsSomeone has to install all of it.
Worth understandingElectrical contractors are the quiet beneficiaries of the entire buildout. They are not a technology story so they attract little attention, but every megawatt installed passes through them — and unlike almost everything else in this tree, their work cannot be done offshore or in advance.
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L3 · bedrock · serves branches 4, 5
Skilled electrical labour
bedrock
Why it existsA trained electrical workforce cannot be expanded on demand. Apprenticeships take years; the trades were not sized for this.
Worth understandingOf all the bedrock in this tree, this is the only one that cannot be addressed by anyone spending any amount. A fab can be built. A substrate supplier can be qualified over a decade. A journeyman electrician takes the time it takes.
And it is shared: the same workforce commissions the liquid cooling loops on branch 4. Exposure spread across "power equipment" and "data centre construction" shares a bedrock, which is the sharpest illustration in the tree of why convergence matters more than diversification across branches.
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Reading this branch
It is short, and it does not bind on its own. Three rings, and the tightness at every one is inherited from branch 4 rather than generated here.
Its bedrock is people, and it is shared. Of all the bedrock in this tree, skilled electrical labour is the only one that cannot be addressed by anyone spending any amount. A fab can be built; a substrate supplier can be qualified over a decade; a journeyman electrician takes the time it takes.
It absorbs the delays from everywhere above it, which makes it a useful place to observe whether the rest of the tree is actually converting. Announcements accumulate upstream. Buildings either exist or they do not.