Arithmetic

Why it exists

The tested logic die performs the matrix multiplications. It is the semiconductor component people usually mean when they say "AI chip," before HBM, interposer and substrate turn it into a usable accelerator package.

NVIDIA holds roughly 70-75% of data centre AI accelerator revenue in 2026, down from a peak near 87% in 2024. The custom side runs through two co-design houses: Broadcom at roughly 70-75% of custom ASIC co-design (Google TPU, Meta MTIA) and Marvell at 20-25% (AWS Trainium and Inferentia, Microsoft Maia) — together about 95% of that market. Tom's Hardware, custom ASIC state of play.

Not constrained by design or fabrication capacity. Logic die can exist in inventory while the accelerator cannot ship because HBM or an integration slot is missing. That is why the die and the package are separate nodes.

Relevant businesses

• NVIDIA
• AMD
• Broadcom
• Marvell

Worth understanding

Custom ASIC shipments are outgrowing merchant GPUs for the first time — TrendForce projects 44.6% against 16.1% in 2026. That matters to the map in a specific way: custom programs sit second in the queue for constrained inputs. When packaging or memory is short, the vendor with the largest committed volume is served first. The custom-silicon story and the bottleneck story are entangled, not independent.

Why it exists

A logic die is not yet an installable accelerator. Advanced-package integration joins it to qualified HBM and the interposer/substrate stack; the resulting package is the component that a server board and liquid-cooled rack can actually accept.

This is an output node, not another fabrication bottleneck. Its availability inherits the scarcest of the streams that meet immediately before it. More logic die do not create more accelerator packages when HBM allocation is fixed, and more packaging slots do not help when qualified HBM is missing.

Relevant businesses

• NVIDIA
• AMD
• custom-ASIC owners
• TSMC and OSAT partners

Worth understanding

Keeping the package separate prevents a common category error: treating “GPU supply” as though it were wafer supply. The commercial unit crosses several independently scheduled production systems before it reaches an ODM.

Why it exists

Nobody designs a leading-edge accelerator from nothing. Co-design capability, EDA tools and licensed processor/interconnect IP turn an architecture into a manufacturable tape-out.

Synopsys and Cadence are an EDA duopoly with Siemens EDA third. Arm supplies CPU IP. The high-speed SerDes that moves data between chips is a chokepoint of expertise rather than capacity.

Not constrained in any capacity sense — software has no lead time. But it is a rent-capturing layer with extraordinary economics and near-total switching-cost lock-in.

Relevant businesses

• Synopsys
• Cadence
• Arm
• Alphawave
• Rambus

Worth understanding

This node is the cleanest proof in the map that tightness and rent are separate variables. EDA gates nothing and earns enormously. Any framework that equates "bottleneck" with "where the money is" fails here immediately.

Why it exists

The design has to become silicon, at N3 today and N2 next.

TSMC, and effectively only TSMC for leading-edge AI silicon. Samsung and Intel matter for optionality and for policy, both structurally behind at the leading edge.

Tight, but not the gate. This is the correction to make early, because the popular mental model is still "the shortage is chips." Wafer capacity at N3/N5 is not what limits AI accelerator supply. Packaging and memory are, which is branch 2.

Relevant businesses

• TSMC
• Samsung Foundry
• Intel Foundry

Worth understanding

The industry solved the wafer problem before it solved the assembly problem. A leading-edge fab is enormously expensive but well-understood and has been scaling for decades. What sits on branch 2 is newer, less automated, and was not built for this volume.

The same company may also fabricate switch ASICs or integrate HBM, but those are different production paths with different process requirements and queues. The map therefore names this node by the product it enables rather than using TSMC as a proxy for three nodes.

Why it exists

Fabs are assembled from tools, and the tools have longer lead times than the fabs do.

Deposition and etch are supplied by Applied Materials, Lam Research and Tokyo Electron; metrology and process control by KLA. Lithography is separated because EUV has a different supplier structure and expansion clock.

Relevant businesses

• Applied Materials
• Lam
• Tokyo Electron
• KLA

Worth understanding

“Fab equipment” is not one market. This node covers the non-lithography tool set used on the accelerator wafer path; HBM bonding tools and compound-semiconductor epitaxy sit with the products they specifically enable.

Why it exists

Every die has to be verified before it goes into a package that costs more than the die does.

Tight, and the most plausible candidate for the next silicon-side bottleneck nobody is watching.

Relevant businesses

• Advantest
• Teradyne
• Aehr
• Camtek
• Onto

Worth understanding

AI accelerators are enormous die with long test times, and test capacity scales with neither wafer starts nor packaging capacity. It is a separate queue with its own equipment lead times, and it becomes visible the moment the two constraints in front of it clear. If branches 2 and 3 resolve on schedule in 2027-28, this is the most likely thing standing behind them.

Why it exists

The fab consumes polished silicon wafers, photoresist, specialty gases and ultrapure chemicals.

Not constrained. Standard silicon wafers are not the problem anywhere on this map. The compound substrates that are a problem sit on the movement path, not here — a distinction worth holding because “wafer supply” language gets applied to both.

Relevant businesses

• Shin-Etsu
• SUMCO
• GlobalWafers
• JSR
• Entegris

Why it exists

Below a certain feature size there is no other way to pattern a wafer.

ASML says it is raising capacity roughly 30% in each of the next two years, cutting EUV build-and-test cycle time from about 22 weeks toward 15 or 16, and is close to fully booked on EUV for 2027 with a substantial 2028 order book. Component shortages inside its own supply chain still limit output.

Relevant businesses

• ASML alone

Worth understanding

When the tool vendor is booked two years out, capacity decisions taken today do not produce wafers until 2028. That sets the outer bound on how fast anything downstream can expand — on this branch and on branch 2, because leading-edge DRAM now needs EUV too.

This is a monopoly of accumulated expertise rather than of capacity, which behaves differently from a full order book. An order book clears when capacity arrives. An expertise monopoly does not clear at all; it just becomes less binding when demand growth slows. That makes it the most durable position on this branch and simultaneously the one least likely to be mispriced, since everybody already knows.

Why it exists

ASML does not make the hardest parts of its own machine. The mirrors — the flattest surfaces manufactured anywhere — come from Carl Zeiss SMT, and the high-power CO₂ drive lasers from Trumpf, with the light source itself from ASML's own Cymer.

Relevant businesses

• Carl Zeiss SMT
• Trumpf
• Cymer (ASML-owned)

Worth understanding

The projection optics are one supplier deep, while the drive-laser and source subsystems have their own concentrated owners. Keeping them bundled here is a map-resolution choice: they jointly enable the EUV tool, but the detail preserves that they are parallel subsystems rather than one product or one company.

It is also the clearest demonstration of why deriving the path beats enumerating parts. Nothing about Zeiss would ever surface in a screen of AI companies, and its subsystem sits upstream of every leading-edge accelerator wafer.